xavier pci
xavier pci endport
Jetson xavierのpcie の一部がendport(以下ep)機能も持ったdual mode portである。DTS(Device Tree Source)の下記C0,C4,C5がep機能を持つ。DTSでepをenableする場合、root port(以下rp)側をdisableする必要がある。
dts config
- pcie_ep@14180000 for C0
- pcie_ep@14160000 for C4
- pcie_ep@141a0000 for C5
Xavier Dev kit では、下記に利用している。
C0 : m.2 key m
C5 : pcie slot
odmdata
Please set BIT:12 of ODM data to enable PCIe EndPoint mode ODMDATA=0x9191000;
The file you need to change should be "p2972-0000.conf.common"
Carrier board
xavier
- p2822
- p2888
- p2972 @ 2019/05頃?
article
Only C5 controller can be used as it can own open slot Two Xavier devkit boards are required with one configured for C5's RP operation and other configured for C5's EP operation Need finger-to-finger card to connect two devkits using their PCIe x8/x16 open slot Please flash one devkit with default ODM data to operate C5 in Root port mode and other with bit-12 set to '1' to operate C5 in Endpoint mode
art2
source
FWIW, there are three controllers C0, C4 and C5 which can operate in end point mode (one at a time) and corresponding device-tree nodes are already available. Please enable pcie_ep@14180000 for C0 pcie_ep@14160000 for C4 pcie_ep@141a0000 for C5 and disable their corresponding root port nodes There is a platform driver (pcie-tegra-dw-ep.c) available to configure controller for endpoint mode of operation and also a client driver (tegra-pcie-ep-mem.c) to exercise the DMA functionality of end point controller. You can write your own client driver to satisfy your requirements and modify platform driver also accordingly.
pci express configuration space
Enhanced Configuration Address Mapping
| Memory Address bits | Field |
|---|---|
| 27:24 | offset high 4bit |
| 23:16 | Bus |
| 15:11 | Device |
| 10:8 | Function |
| 7:2 | Extended Reg num. |
| 1:0 | Byres |
bus n : 1 to 8
regnum 6bitから、64 registers.
