save and restore

vcsでsave, restore を使い、uvmシミュレーションの初期化部分実行後にsave, その他の試験をrestore 後に実行する。

実行イメージ

# build
vcs -sverilog -ntb_opts uvm a.sv -debug

# init and save
./simv +UVM_TESTNAME=general  -ucli -i init.in

# run test with seq1 to 3
./simv +seq=seq1 -ucli -i  continue.in
./simv +seq=seq2 -ucli -i  continue.in
./simv +seq=seq3 -ucli -i  continue.in

init.in

run 100
save init.save
quit

continue.in

restore init.save
run

a.sv testbench top
build -debug option 付きで実行. -debug でucli を有効にする。
init 初期化後にucliにてsave. -i filenameファイルからucliコマンドを受け取る。
run restore後に、plusarg seqに試験名を設定して実行。

ベリログ側

class t extends uvm_test;

  `uvm_components_utils(t)
  // ...
  task reset_phase(uvm_phase phase);
    phase.raise_objectuon(this)
    #100
    phase.drop_objection(this)
  endtask : reset_phase
endclass : t

sequencer がtb.src.sequencerとする。 plusarg で渡すsequence名が別途定義されている事。

class general extends t;
   `uvm_components_utils(general)
    // ...
    virtual task main_phase(uvm_phase phase);
      uvm_sequence_base s;
      string name;

      phase.raise_objection(this);
      super.main_phase(phase);

      if ( $test$plusarg("seq")) begin
        $value$plusarg("seq=%s", name);
      end

      $cast(s, factory.create_object_by_name(name));

      s.start( tb.src.sequencer );

      phase.drop_objection(this);

    endtask : main_phase

endclass : general

補足

uvm run_phaseのサブフェーズ。

reset, configure, main, shutdownに、それぞれpreとpostの12フェーズ。

Contents

UVM Run-Time PhasesThe run-time schedule is the pre-defined phase schedule which runs concurrently to the uvm_run_phase global run phase.

phase	description
uvm_pre_reset_phase	Before reset is asserted.
uvm_reset_phase	Reset is asserted.
uvm_post_reset_phase	After reset is de-asserted.
uvm_pre_configure_phase	Before the DUT is configured by the SW.
uvm_configure_phase	The SW configures the DUT.
uvm_post_configure_phase	After the SW has configured the DUT.
uvm_pre_main_phase	Before the primary test stimulus starts.
uvm_main_phase	Primary test stimulus.
uvm_post_main_phase	After enough of the primary test stimulus.
uvm_pre_shutdown_phase	Before things settle down.
uvm_shutdown_phase	Letting things settle down.
uvm_post_shutdown_phase	After things have settled down.