Fermi / GF100 Architecture

Structure

• 1 GPU = 4 GPC
• 1 GPC = 4 SM + 1 Rasterizer
• 1 SM = 32 SP + 1 Tesserator + 1 Dual- issue per 2 cycle instruction unit + 4 SFU + 16 load store unit
• SP = CUDA core
• 1 SP = 2issue,

GF100

GF100 = 4GPC = 4x4SM = 4x4x 32 CUDA core = 512 core

rasterizer

Edge setup - rasterizer - z-cull

tessellator / polymorph engine

virtex fetch - tessellator - view port transform - attribute setup - streamout

GPC image

ref

https://pc.watch.impress.co.jp/docs/column/kaigai/343352.html

GP100

PASCAL

1GPU = 6 GPC 1GPC = 10SMX 1SMX = 32 CORE

1GPU = 1920 core 1GPC = 320 CORE

gv100 volta

• 6 gpc/ chip
• 14 sm/ gpc

• 64 cotes/sm

• 84sm/chip

• 5376cores/chip

84= 3x7x2²

GPC history

• Fermi 2009/11/6 published
• Kepler 2012/5/16 publushed 1SMX = 192 CUDA core Maxwell
  Pascal 2016/6 published Volta 2017/5 published Turing