初めに

UVMでは一つのモデルで複数の試験を可能にするため、simulatorからモデルに試験名を渡す事ができる。

一般的にmodel側でrun_test() を実行する際の引数=試験名をsimulator の+UVM_TSTNAME=試験名オプションで渡す。

以下は以下はサンプルを示す。

uvm hello world

programを使ってはいけないと言う記事を読んだ事があるが理由不明。取り敢えず、例ではprogramだが、moduleに変えた方が無難。

programを使った例

test1.sv

program automatic test_program; //can be a module

 import uvm_pkg::*;

  initial begin

 `uvm_info("DEMO", "HelloWorld!", UVM_MEDIUM); //macro

 end

endprogram

uvm_testを使った例

Using other 3 service mechanisms in code> Test Example:

test2.sv

program automatic test_program; //can be a module

 import uvm_pkg::*;


class hello_world_test extends uvm_test;

 `uvm_component_utils(hello_world_test)

 function new(string name, uvm_component parent);

  super.new(name, parent);

 endfunction


  virtual task run_phase(uvm_phase phase); 

  //the run_phase method will be executed automatically by the UVM simulation manager

 `uvm_info("DEMO", "HelloWorld!", UVM_MEDIUM); //macro

  endtask

 endclass

 initial begin 
    //to enable UVM route (to automatically enable) for you

   run_test();

 end

endprogram

実行

# After Compilation (vcs): 
vcs -sverilog -ntb_opts uvm test2.sv
# Simulate with:
simv +UVM_TESTNAME=hello_world_test

configuratuon DBを使った場合

UVM Configuration Database Example: Here, instead of "Hello World" a string variable msg is used. Compilation and Simulation will produce the same result. But now, we can use a UVM runtime switch to change the message to what we want for that simulation without running another test.

The uvm_config_db requires 3 arguments. 1> Specifies name of the uvm object you want to configure.

test3.sv

program automatic test_program; //can be a module

 import uvm_pkg::*;


class hello_world_test extends uvm_test;

 `uvm_component_utils(hello_world_test)
 String msg;

 function new(string name, uvm_component parent);

  super.new(name, parent);

  msg = "Hello World!";
 endfunction

  virtual task run_phase(uvm_phase phase); 

//the run_phase method will be executed  automatically by the UVM simulation  manager

uvm_config_db#(string)::get(this/*Target*/, "", "message", msg);
 `uvm_info("DEMO", msg, UVM_MEDIUM);

  endtask

 endclass

 initial begin

  //to enable UVM route (to automatically enable) for you

  run_test();

 end

endprogram

実行

# Simulate with:

simv +UVM_TESTNAME=hello_world_test \

+uvm_set_config_string=uvm_test_top,message,New\ World!

Arguments:

uvm_test_top = Target

message = Database entry key => It must match with the 3rd argument of the get method -- get(). The Retrieval from the Database is based on this entry key.

Set value = the Last argument that you want to store in the Database. If the target and the entry key matches, then you get the Result.

uvm test modelsim_aseの場合。

vlib workset

# set class lib
uvm=/opt/uvm/src

vlog -sv $dir/uvm_pkg.sv +incdir+$uvm +define+UVM_HDL_NO_DPI+UVM_NO_DPI+UVM_CMDLINE_NO_DPI+UVM_REGEX_NO_DPI

defineはUVMのDPI動作モードをOFFにするため。modelsim-aseにおいて、DPI単体の動作確認はできているが、UVMに含まれるDPI周りの機能はうまく有効化できなかったので、 OFFにします。

注：コンパイルすると、Warningが出ます。これは、UVMが使用しているSystemVerilogのrandomizeメソッドをmodelsim-aseがサポートしていないためです。randomizeメソッド周りの動作は使えませんが、使えなくてもUVMの恩恵はある程度受けられます。

UVMをテストベンチに組み込む。次のファイルを作成します。

tb_top.sv

`timescale 1ps/1ps

module tb_top; 

`include "uvm_macros.svh" 

import uvm_pkg::*;

endmodule

コンパイル、ラン。

vlog -sv +incdir+$uvm  tb_top.sv

vsim -c tb_top -do "run -all;quit"

# run -all
# -------------------------------------------------------------
# UVM
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# -------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled

# with `UVM_NO_DEPRECATED undefined.

# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled

# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.

# See http://www.eda.org/svdb/view.php?id=3770 for more details.

#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# quit

UVMでHello World

試験。class uvm_test のサブクラスに定義。

tb_top.sv

`timescale 1ps/1ps

module tb_top; 

  `include "uvm_macros.svh" 
  import uvm_pkg::*;

  class hello extends uvm_test;

    `uvm_component_utils(hello)

    function new (
      string name="hello",     
      uvm_component parent=null  ); 

      super.new(name,parent); 

    endfunction 

    task run_phase(uvm_phase phase);
      uvm_report_info("TEST", "Hello World"); 
    endtask

  endclass

  initial begin 
    run_test("hello");
    // run_test()  // usually use this 
  end

endmodule

compile and run

vlog -sv +incdir+$uvm  tb_top.sv

vsim -c tb_top -do “run -all;quit”

# UVM_INFO @ 0: reporter [RNTST] Running test hello...
# UVM_INFO @ 0: uvm_test_top [TEST] Hello World

テスト名を実行時に渡す為、run_testの引数を削除。

initial begin 
  run_test();
end

実行時にテスト名を渡す。

vlog -sv +incdir+$uvm  tb_top.sv

vsim -c tb_top +UVM_TESTNAME=hello -do “run -all;quit”

# UVM_INFO /opt/uvm/src/base/uvm_root.svh(370) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
# UVM_INFO @ 0: reporter [RNTST] Running test hello...
# UVM_INFO @ 0: uvm_test_top [TEST] Hello World

エラー例

不正なuvm_testname 時

vsim -c tb_top +UVM_TESTNAME=mhello -do “run -all;quit”

# UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'mhello' because it is not registered with the factory.

# UVM_FATAL @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=mhello not found.